Munich, July 2023 – Looking back at this year’s FPGA Conference Europe, we have gained a lot of insights on standardizing FPGA. There is a broad consensus in the FPGA market, that there is a need for something to standardize FPGA to some extent. Not only for hardware, but also for configuration and software. Which is exactly what we as SGET have been working on for the last 18 months. And by presenting our ideas to the experienced audience at FPGA Conference Europe, we wanted to see, if our ideas are interesting to the key-players as well as to the users in the FPGA industry.
On the second day of the show, we were to hold a presentation, taken to stage by our Chairman Ansgar Hein. He introduced three different approaches towards a possible FPGA standard, generated by several SGET members, such as iWave, Enclustra, Aries Embedded and Trenz, in his talk on “Maximizing Efficiency – The importance of FPGA Standardization” to an audience of around 60 participants. But the discussion did not stop there, but went on throughout the whole evening and ended around 9pm with lots of feedback, insights and ideas for an Open FGPA Standard.
The three different proposals are:
- #01: OSM based mdoular design
Solder-on modules (SoC), suitable for Entry- to Mid-Range FPGAs with 332 – 1226 pins and up to ~650k logic elements and with different sizes, ranging from Size-S (30 mm x 30 mm) to Size-XXL (60 mm x 60 mm) and different pin-out options (i.e. Size-XL with 923 or 875 pins).
- #02: Connector based design
Based on ADM6-60 connectors and following the Andromeda SoC layout, Mid- to High-Range FPGA can be targett with focus on high-speed and high-profile applications. Small form-factor (40 mm x 56 mm) up to larger form-factors (80 mm x 64 mm) with varying amount of board-connectors and with upt to 686 user I/Os.
- #03: Mixed mode (solder-on and connectors)
Goal is to simplify the application of Mid-Range FPGA, reduce base-board costs (design efforts, BOM, PCB) and project risks. Suitable for FPGA Package sizes from 15 x 15 mm to 35 x 35 mm. Standard should be self-containing (basic functionality only), scalable (between module & baseboard) and flexible (uncommitted / unrestricted I/O pins).
If you are interested in more details, please download the presentation below. And if you are into FPGA and interested in joining our closed discussion group, please let us know.